1. Field of the Invention
This invention relates to a sample and hold circuit for sampling the instantaneous voltage of an analogue input signal and holding the sampled voltage at the output and more particularly, to a sample and hold circuit employing a metal-oxide semiconductor (MOS) transistor as a sampling switch and a capacitor as a holding means.
2. Description of the Prior Art
In general, a sample and hold circuit (hereinafter referred to as a S/H circuit) is comprised of a sampling switch and a holding capacitor. One end of the switch is connected to an input terminal of the circuit and another end of the switch is connected to an output terminal of the circuit as well as to the capacitor. An analogue signal is applied to the input signal. When the switch is turned on, the capacitor is charged, i.e. sampling is effected. After the sampling, the voltage is held even when the switch is turned off. Thus, the sampled voltage of an analogue signal is converted to a constantly held voltage. This technique is applied in, for example, an A/D converter.
In such a S/H circuit, it is important that the output voltage does not vary before and after turning off the switch. However, where a Metal Oxide Semiconductor (MOS) transistor is used as the sampling switch, there is a problem in that the output voltage is changed by switching the MOS transistor from an on state to an off state. The MOS transistor is comprised of a gate, a source, a drain, and a bulk silicon under the gate. The drain (or source) is connected to the input terminal of the S/H circuit, the source (or drain) is connected to the output terminal of the S/H circuit and to the holding capacitor, and the gate is used as a switching terminal. The MOS transistor is switched from the on state to the off state or vice versa by changing the control voltage applied to the state. The above-mentioned change of the output voltage is based on the following two causes. The first cause is that the control voltage applied to the gate in the on state is different from the control voltage in the off state, and the parasitic gate-source capacitance partially couples the control voltage change to the output terminal. The second cause is that the channel region formed between the source and the drain during the on state disappears in the off state, and the charge stored in the carriers must be dispersed.
In the prior art, in order to avoid voltage change at the output terminal, a dummy capacitor, which has the same capacity as the parasitic capacitor between the gate and the source of the MOS transistor is used. The dummy capacitor is connected, through an inverter, between the gate and the source outside and the MOS transistor. By this arrangement, the first cause of the above mentioned problem is in theory eliminated, as hereinafter described in detail. However, it is difficult in the manufacturing process to make the dummy capacitor have the same capacitance as the parasitic capacitor between the gate and the source in the MOS transistor. Therefore, in practice, the output voltage usually changes before and after the turning off of the MOS transistor. In addition, in this prior art circuit, the above-mentioned second cause is not taken into account.